(PR) Lexar Shows New AI Storage Core Technologies and Storage for Specialized
Beyond portable storage, Lexar is also showcasing the continued evolution of its AI Storage Core at IFA 2026. Combining advanced packaging, chip hardware, Lexar Luma Bridge technologies, and system-level optimization…
Beyond portable storage, Lexar is also showcasing the continued evolution of its AI Storage Core at IFA 2026. Combining advanced packaging, chip hardware, Lexar Luma Bridge technologies, and system-level optimization, the showcase includes next-generation AI-grade Gen 5 SSD and AI-grade Gen 5 Storage Stick. With bandwidth of up to 11 GB/s, these concepts support compact AI devices requiring larger local model storage, faster model switching, lower-latency data access, and sustained performance within constrained power and thermal environments.
Underpinning these concepts is an integrated hardware-software architecture built around Longsys' self-developed Gen 5 controller SPU, or Storage Processing Unit, and Lexar Luma Bridge technologies. Manufactured on an advanced 5 nm process with a DRAM-less architecture, the SPU is engineered to improve supply stability while maintaining high-performance AI storage capabilities. Lexar Luma Bridge uses intelligent workload scheduling, predictive prefetch, and optimized cache management to address large Mixture-of-Experts models, expanding KV Cache, and I/O latency—improving local AI performance while reducing DRAM capacity requirements by approximately 40%. Read full story
Underpinning these concepts is an integrated hardware-software architecture built around Longsys' self-developed Gen 5 controller SPU, or Storage Processing Unit, and Lexar Luma Bridge technologies. Manufactured on an advanced 5 nm process with a DRAM-less architecture, the SPU is engineered to improve supply stability while maintaining high-performance AI storage capabilities. Lexar Luma Bridge uses intelligent workload scheduling, predictive prefetch, and optimized cache management to address large Mixture-of-Experts models, expanding KV Cache, and I/O latency—improving local AI performance while reducing DRAM capacity requirements by approximately 40%. Read full story